An application of partial scan techniques to a high-end system LSI design

被引：0
|
作者：
Ono, T [1 ]
Kozawa, A [1 ]
Kimura, T [1 ]
Konno, Y [1 ]
Saga, K [1 ]
机构：
[1] NEC Corp Ltd, Tsukuba, Ibaraki, Japan
来源：
10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS | 2001年
关键词：
D O I：
10.1109/ATS.2001.990329
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An overview is given on several techniques for effectively applying partial scan DFT to a large high-speed system LSI. Advantages of the partial scan method are highlighted with these techniques while controlling its disadvantages, such as pattern length and ATPG time.
引用
收藏
页码：459 / 459
页数：1
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