Speed superiority of scaled double-gate CMOS

被引：61

作者：

Fossum, JG ^{[1
]}

Ge, LX

Chiang, MH

机构：

[1] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA

[2] Adv Micro Devices Inc, Sunnyvale, CA 94088 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2002年 / 49卷 / 05期

关键词：

CMOS modeling; double-gate MOSFETs; gate capacitance; propagation delay; on-state current;

D O I：

10.1109/16.998588

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Unloaded ring-oscillator simulations, done with a generic process/physics- based compact model for double-gate (DG) MOSFETs and supplemented with model-predicted on-state currents and gate capacitances for varying supply voltages (V-DD), are used to show and explain the speed superiority of extremely scaled DG CMOS over the single-gate (e.g., bulk-Si) counterpart. The DG superiority for unloaded circuits is most substantive for low VDD < similar to1 V.

引用

页码：808 / 811

页数：4

共 50 条

[1] Extremely-scaled double-gate CMOS with non-self-aligned back gate
Kim, K
Hanafi, HI
Cai, J
Chuang, CT
2005 IEEE VLSI-TSA INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY (VLSI-TSA-TECH), PROCEEDINGS OF TECHNICAL PAPERS, 2005, : 110 - 111
[2] HIGH-SPEED AND LOW-POWER N(+)-P(+) DOUBLE-GATE SOI CMOS
SUZUKI, K
TANAKA, T
TOSAKA, Y
HORIE, H
SUGII, T
IEICE TRANSACTIONS ON ELECTRONICS, 1995, E78C (04) : 360 - 367
[3] Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices
Kim, K
Fossum, JG
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (02) : 294 - 299
[4] Small Signal Modeling of Scaled Double-Gate MOSFET for GHz Applications
Sood, Himangi
Srivastava, Viranjay M.
Singh, Ghanshyam
INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS, 2017, 47 (01): : 14 - 23
[5] Optimization of source/drain extension for robust speed performance to process variation in undoped double-gate CMOS
Yang, Ji-Woon
Pham, Daniel
Zeitzoff, Peter
Huff, Howard
Brown, George
2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS, 2006, : 48 - +
[6] Extremely scaled double-gate CMOS performance projections, including GIDL-controlled off-state current
Fossum, JG
Kim, K
Chong, Y
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (11) : 2195 - 2200
[7] CMOS-Based Biosensors with an Independent Double-Gate FinFET
Ahn, Jae-Hyuk
Kim, Jee-Yeon
Jung, Cheulhee
Moon, Dong-Il
Choi, Sung-Jin
Kim, Chang-Hoon
Lee, Kyung-Bok
Park, Hyun Gyu
Choi, Yang-Kyu
2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2011,
[8] Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs
Liu, Liu
Kumar, Shubham
Thomann, Simon
Anirouch, Hussam
Hu, Xiaobo Sharon
2023 60TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC, 2023,
[9] Double-gate finFETs as a CMOS technology downscaling option: An RF perspective
Nuttinck, Sebastien
Parvais, Bertrand
Curatola, Gilberto
Mercha, Abdelkarim
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (02) : 279 - 283
[10] A simple modelling of device speed in double-gate SOI MOSFETs
Rajendran, K
Samudra, G
MICROELECTRONICS JOURNAL, 2000, 31 (04) : 255 - 259

← 1 2 3 4 5 →