VLTI fringe tracking real time computer architecture

Fringe tracking is a CPU intensive real time application. Rates of up to 1 KHz are needed to be able to freeze the atmosphere; in addition, each available baseline must be tracked independently. To be able to overcome the CPU performance limits, VLTI 1st generation trackers PRIMA fringe sensor unit (FSU) (7, 20) and FINITO (2, 20) were implemented in a distributed architecture separating the sensor from the controller. A side effect of this design was that the control loop delay increases as the system runs asynchronously causing an increase of the phase RMS value. This is in conflict with the objective of stabilizing the fringes with the smallest possible phase RMS. VLTI 2nd generation trackers (GRAVITY (6) and ESO 2GFT) currently being designed, will operate with up to six baselines and need to achieve phase RMS values smaller than 200 [nm]. This paper will present the computer architecture of the first generation trackers. Using simulations carried out in the PRIMA testbed 12, the induction of phase RMS by additional pure delays of the control loop will be precisely quantify. Afterwards, using the current architecture as reference, expected values of pure delays will be estimated for a six baselines tracker. Finally, an in order to overcome this problem, a new design that exploits the inherent parallelism of the multiples baselines and integrates the sensor and the controller in a single computer will be briefly proposed.