An IR-Drop Aware Test Pattern Generator for Scan-Based At-Speed Testing

The excessive circuit switching activity during scan-based at-speed testing has been known to cause yield loss because it degrades the circuit performance and can cause a good device to fail the test. In this paper, we propose an IR-drop aware test pattern generator to produce high-quality at-speed test patterns. The idea is to manage the switching activity distribution of the generated test patterns so that the resulting IR-drop profiles match the user-specified ones. To improve the efficiency of the IR-drop matching process, the maximum-implication random-fill (MIR-fill) based IR-drop matching technique is developed. Simulation results show that the proposed test pattern generator achieves 20 times speedup compared to the previous work and also delivers significant IR-drop cost reduction.