On the implementation of a low-power IEEE 802.11 a compliant Viterbi decoder

被引：0

作者：

Maharatna, K ^{[1
]}

Troya, A ^{[1
]}

Krstic, M ^{[1
]}

Grass, E ^{[1
]}

机构：

[1] Univ Bristol, Bristol BS8 1TH, Avon, England

来源：

19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have been used to reduce the power consumption and the inherent bandwidth mismatch between the Add-Compare-Select (ACS) and traceback operations. Aggressive clock gating and innovative circuit techniques reduce the power consumption further. The normalized cell area and dynamic power consumption of the designed VD are 5.9 mm(2) and 53 mW respectively. The normalized power dissipation of the VD is 0.66 mW/Mbps.

引用

页码：613 / 618

页数：6

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