Design of a Reconfigurable Chaos Gate with Enhanced Functionality Space in 65nm CMOS

被引：0

作者：

Shanta, Aysha S. ^{[1
]}

Majumder, Md. Badruddoja ^{[1
]}

Hasan, Md Sakib ^{[1
]}

Uddin, Mesbah ^{[1
]}

Rose, Garrett S. ^{[1
]}

机构：

[1] Univ Tennessee, Dept Elect Engn & Comp Sci, Knoxville, TN 37996 USA

来源：

2018 IEEE 61ST INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2018年

关键词：

Chaos computing; logic obfuscation; CMOS; VLSI; hardware security; IMPLEMENTATION;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a three transistor circuit has been implemented in a standard 65 nm CMOS technology. The circuit has been used as a map to generate discrete-time chaotic signals. The map circuit has been combined with another map circuit in order to build a chaotic generator. The circuit is compact since it uses only twelve transistors in total to generate different Boolean functions as part of a chaotic computer. The total power consumption of the chaotic generator is only 18.4 mu W and the area is 0.556 mu m(2). The circuit can be used as a logic gate and has been designed to generate various functions using multiple configurations. The number of functionalities of the chaos gate has been increased by altering the bias and threshold voltages.

引用

页码：1016 / 1019

页数：4

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