A Retention-Aware Multilevel Cell Phase Change Memory Program Evaluation Metric

被引：6

作者：

Khwa, Win-San ^{[1
,2
]}

Chang, Meng-Fan ^{[2
]}

Wu, Jau-Yi ^{[1
]}

Lee, Ming-Hsiu ^{[1
]}

Su, Tzu-Hsiang ^{[1
]}

Wang, Tien-Yen ^{[1
]}

Li, Hsiang-Pang ^{[1
]}

BrightSky, Matthew ^{[3
]}

Kim, SangBum ^{[3
]}

Lung, Hsiang-Lan ^{[1
]}

Lam, Chung ^{[3
]}

机构：

[1] Macronix Int Co Ltd, Hsinchu 30078, Taiwan

[2] Natl Tsing Hua Univ, Hsinchu 30013, Taiwan

[3] IBM TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 2016年 / 37卷 / 11期

关键词：

Phase change memory; multiple-level cell; programming scheme; resistance drift; RELAXATION; RESISTANCE; DRIFT;

D O I：

10.1109/LED.2016.2614513

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Multilevel cell (MLC) phase change memory (PCM) offers many potential advantages in scalability, bit-alterability, non-volatility, and high program speed. While many program approaches had been proposed, they were usually evaluated in energy, delay, or energy-delay product (EDP). These metrics, however, often overlook the data integrity maintenance (DIM) overhead caused by the resistance drift (R-drift) phenomenon in the MLC PCM. This letter proposes a programmaintenance (PM) metric, which is a modified EDP metric with DIM consideration. Furthermore, we evaluated the PM metric of various pulse shapes in iterative program-verify scheme. From the measured data of a 128M-cell MLC PCM chip, we showed that the PM metric of optimized pulse shape is better than those of the conventional SET and RESET pulse shapes up to 86.7%.

引用

页码：1422 / 1425

页数：4

共 50 条

[31] A Time-Aware Fault Tolerance Scheme to Improve Reliability of Multilevel Phase-Change Memory in the Presence of Significant Resistance Drift
Xu, Wei
Zhang, Tong
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (08) : 1357 - 1367
[32] Fault-Aware Dependability Enhancement Techniques for Phase Change Memory
Lu, Shyue-Kung
Li, Hui-Ping
Miyase, Kohei
Hsu, Chun-Lung
Sun, Chi-Tien
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2021, 37 (04): : 503 - 513
[33] Content-Aware Reduction of Bit Flips in Phase Change Memory
Kulandai Sj, Arockia David Roy
Schwarz Sj, Thomas
IEEE Letters of the Computer Society, 2020, 3 (02): : 58 - 61
[34] Fault-Aware Dependability Enhancement Techniques for Phase Change Memory
Shyue-Kung Lu
Hui-Ping Li
Kohei Miyase
Chun-Lung Hsu
Chi-Tien Sun
Journal of Electronic Testing, 2021, 37 : 503 - 513
[35] Investigation of Data Retention under Current Bias for Phase Change Memory
Lu Yao-Yao
Cai Dao-Lin
Chen Yi-Feng
Wang Yue-Qing
Wei Hong-Yang
Huo Ru-Ru
Song Zhi-Tang
2016 INTERNATIONAL WORKSHOP ON INFORMATION DATA STORAGE AND TENTH INTERNATIONAL SYMPOSIUM ON OPTICAL STORAGE, 2016, 9818
[36] Cell design considerations for phase change memory as a universal memory
Lam, Chung
2008 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PROGRAM, 2008, : 132 - 133
[37] Te-free SiSb phase change material for high data retention phase change memory application
Zhang, Ting
Song, Zhitang
Wang, Feng
Liu, B.O.
Feng, Songlin
Chen, Bomy
Japanese Journal of Applied Physics, Part 2: Letters, 2007, 46 (25-28):
[38] Te-free SiSb phase change material for high data retention phase change memory application
Zhang, Ting
Song, Zhitang
Wang, Feng
Liu, Bo
Feng, Songlin
Chen, Bomy
JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2007, 46 (25-28): : L602 - L604
[39] Multilevel storage in lateral top-heater phase-change memory
Yin, You
Ota, Kazuhiro
Higano, Naoya
Sone, Hayato
Hosaka, Sumio
IEEE ELECTRON DEVICE LETTERS, 2008, 29 (08) : 876 - 878
[40] Applying the Time-Domain Paradigm to Interface Multilevel Phase Change Memory
de Gracia Herranz, Amadeo
Lopez-Vallejo, Marisa
2024 IEEE 24TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY, NANO 2024, 2024, : 405 - 408

← 1 2 3 4 5 →