RONoC: A Reconfigurable Architecture for Application-Specific Optical Network-on-Chip

被引:2
|
作者
Gu, Huaxi [1 ]
Chen, Zheng [1 ]
Yang, Yintang [2 ]
Ding, Hui [1 ]
机构
[1] Xidian Univ, State Key Lab Integrated Serv Networks, Xian 710071, Peoples R China
[2] Xidian Univ, Sch Microelect, Xian 710071, Peoples R China
来源
基金
美国国家科学基金会;
关键词
reconfiguration; optical Network-on-Chip; application-specific; optical router;
D O I
10.1587/transinf.E97.D.142
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Optical Network-on-Chip (ONoC) is a promising emerging technology, which can solve the bottlenecks faced by electrical on-chip interconnection. However, the existing proposals of ONoC are mostly built on fixed topologies, which are not flexible enough to support various applications. To make full use of the limited resource and provide a more efficient approach for resource allocation, RONoC (Reconfigurable Optical Network-on-Chip) is proposed in this letter. The topology can be reconfigured to meet the requirement of different applications. An 8x8 nonblocking router is also designed, together with the communication mechanism. The simulation results show that the saturation load of RONoC is 2 times better than mesh, and the energy consumption is 25% lower than mesh.
引用
收藏
页码:142 / 145
页数:4
相关论文
共 50 条
  • [41] Application-Specific 3D Network-on-Chip Design Using Simulated Allocation
    Zhou, Pingqiang
    Yuh, Ping-Hung
    Sapatnekar, Sachin S.
    2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, : 509 - +
  • [43] Channel allocation protocol for reconfigurable Optical Network-on-Chip
    Luo, Jiating
    Killian, Cedric
    Le Beux, Sebastien
    Chillet, Daniel
    Li, Hui
    O'Connor, Ian
    Sentieys, Olivier
    2015 WORKSHOP ON EXPLOITING SILICON PHOTONICS FOR ENERGY-EFFICIENT HIGH PERFORMANCE COMPUTING (SIPHOTONICS), 2014, : 33 - 39
  • [44] The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation
    Stuart, Matthias Bo
    Stensgaard, Mikkel Bystrup
    Sparso, Jens
    ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2011, 10 (04)
  • [45] Application-specific Memory Performance of a Heterogeneous Reconfigurable Architecture
    Whitty, Sean
    Sahlbach, Henning
    Hurlburt, Brady
    Ernst, Rolf
    Putzke-Roeming, Wolfram
    2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010), 2010, : 387 - 392
  • [46] A Reconfigurable Network-on-Chip Architecture to Improve Overall Performance and Throughput
    Darbani, Paria
    Zarandi, Hamid Reza
    2014 22ND IRANIAN CONFERENCE ON ELECTRICAL ENGINEERING (ICEE), 2014, : 943 - 948
  • [47] A generic network-on-chip architecture for reconfigurable systems:: Implementation and evaluation
    Vestias, Mario P.
    Neto, Horacio C.
    2006 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, 2006, : 737 - 740
  • [48] SHARP: Shared Heterogeneous Architecture with Reconfigurable Photonic Network-on-Chip
    Van Winkle, Scott
    Kodi, Avinash Karanth
    ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2018, 14 (02)
  • [49] Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes
    Chang, Kuel-Chung
    Shen, Jih-Sheng
    Chen, Tien-Fu
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2008, 13 (01)
  • [50] Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis
    Soumya, J.
    Venkatesh, Putta
    Chattopadhyay, Santanu
    2011 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2011, : 341 - 342