Gate sizing to eliminate crosstalk induced timing violation

被引：18
|
作者：
Xiao, T [1 ]
Marek-Sadowska, M [1 ]
机构：
[1] Sun Microsyst Inc, Palo Alto, CA 94303 USA
来源：
2001 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD 2001, PROCEEDINGS | 2001年
关键词：
D O I：
10.1109/ICCD.2001.955023
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Digital circuits manufactured in deep sub-micron technologies may experience crosstalk-induced delay and noise signals. Crosstalk-induced delay can be quite significant and sensitive to the driver strength of coupling neighbors. In this paper we propose gate-sizing techniques to reduce delay in presence of crosstalk effects. The techniques are based oil our previously proposed crosstalk aware static timing analysis. Our experiments show that the proposed techniques are effective and may help designers achieve faster timing closure.
引用
收藏
页码：186 / 191
页数：6
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