Efficient stochastic successive cancellation list decoder for polar codes

被引:2
|
作者
Liang, Xiao [1 ,2 ,3 ,4 ]
Wang, Huizheng [1 ,2 ,3 ,4 ]
Shen, Yifei [1 ,2 ,3 ,4 ]
Zhang, Zaichen [1 ,2 ,3 ,4 ]
You, Xiaohu [1 ,2 ,3 ,4 ]
Zhang, Chuan [1 ,2 ,3 ,4 ]
机构
[1] Southeast Univ, Lab Efficient Architectures Digital Commun & Sign, Nanjing 211100, Peoples R China
[2] Southeast Univ, Natl Mobile Commun Res Lab, Nanjing 211100, Peoples R China
[3] Southeast Univ, Quantum Informat Ctr, Nanjing 211100, Peoples R China
[4] Purple Mt Labs, Nanjing 211100, Peoples R China
基金
中国国家自然科学基金; 国家重点研发计划;
关键词
SCL polar decoder; stochastic computing; 2-bit decoding; distributed sorting; hardware;
D O I
10.1007/s11432-019-2924-6
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Polar codes are one of the most favorable capacity-achieving codes owing to their simple structures and low decoding complexity. Successive cancellation list (SCL) decoders with large list sizes achieve performances very close to those of maximum-likelihood (ML) decoders. However, hardware cost is a severe problem because an SCL decoder with list size L consists of L copies of a successive cancellation (SC) decoder. To address this issue, a stochastic SCL (SSCL) polar decoder is proposed. Although stochastic computing can achieve a good hardware reduction compared with the deterministic one, its straightforward application to an SCL decoder is not well-suited owing to the precision loss and severe latency. Therefore, a doubling probability approach and adaptive distributed sorting (DS) are introduced. A corresponding hardware architecture is also developed. Field programmable gate array (FPGA) results demonstrate that the proposed stochastic SCL polar decoder can achieve a good performance and complexity tradeoff.
引用
收藏
页数:19
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