Using a VHDL testbench for transistor-level simulation and energy calculation

This paper describes a procedure to simulate a transistor-level design using a VHDL testbench. Specifically, the VHDL testbench reads the transistor-level design's outputs and supplies the inputs accordingly. This setup also allows the testbench to check for functional correctness. This type of transistor-level simulation is absolutely necessary for asynchronous circuits because the inputs change relative to handshaking signals, which are not periodic, instead of changing relative to a periodic clock pulse, as do synchronous systems. The method further supports automated calculation of power and energy metrics. This method is first demonstrated using a simple NULL Convention Logic (NCL) sequencer. It is then applied to two more complex NCL circuits, 4-bit x 4-bit unsigned dual-rail and quad-rail non-pipelined multipliers. Energy per operation is automatically calculated and compared for the two different multiplier architectures. An exhaustive testbench is used for both designs to simulate all input combinations; and the testbench checks for functional correctness, showing that both designs produce the desired output for all 256 input combinations.