A Model-driven Validation & Verification Environment for Embedded Systems

被引：0
|
作者：
Gargantini, A. [1 ]
Riccobene, E. [2 ]
Scandurra, P. [2 ]
机构：
[1] Univ Bergamo, DIIMM, Bergamo, Italy
[2] Univ Milan, DTI, Milan, Italy
来源：
2008 INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS | 2008年
关键词：
D O I：
10.1109/SIES.2008.4577708
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
This paper presents a validation and verification tool component, based on the Abstract State Machine formal method, that we are developing to support high level for mal analysis of embedded system model-driven design. This component is integrated into a model-driven environment for HW/SW co-design that provides a graphical high-level representation of HW and SW components by means of UML profiles for SystemC/multi-thread C, and allows C/C++/SystemC code generation/back-annotation from/to graphical UML models.
引用
收藏
页码：241 / +
页数：2
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