A Security Architecture for RISC-V based IoT Devices

被引:0
|
作者
Auer, Lukas [1 ]
Skubich, Christian [2 ]
Hiller, Matthias [1 ]
机构
[1] Fraunhofer Inst Appl & Integrated Secur AISEC, Garching, Germany
[2] Fraunhofer Inst Integrated Circuits IIS, Div Engn Adapt Syst EAS, Dresden, Germany
关键词
RISC-V; device security; secure boot; watchdog timer; IoT;
D O I
10.23919/date.2019.8714822
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
New IoT applications are demanding for more and more performance in embedded devices while their deployment and operation poses strict power constraints. We present the security concept for a customizable Internet of Things (IoT) platform based on the RISC-V ISA and developed by several Fraunhofer Institutes. It integrates a range of peripherals with a scalable computing subsystem as a three dimensional System-in-Package (3D-SiP). The security features aim for a medium security level and target the requirements of the IoT market. Our security architecture extends given implementations to enable secure deployment, operation, and update. Core security features are secure boot, an authenticated watchdog timer, and key management. The Universal Sensor Platform (USeP) SoC is developed for GLOBALFOUNDRIES' 22FDX technology and aims to provide a platform for Small and Medium-sized Enterprises (SMEs) that typically do not have access to advanced microelectronics and integration know-how, and are therefore limited to Commercial Off-The-Shelf (COTS) products.
引用
收藏
页码:1154 / 1159
页数:6
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