Quantum Logic Synthesis with Formal Verification

被引:0
|
作者
Smith, Kaitlin N. [1 ]
Thornton, Mitchell A. [1 ]
机构
[1] Southern Methodist Univ, Dept Elect & Comp Engn, Dallas, TX 75205 USA
关键词
quantum information processing; quantum computing; quantum logic synthesis; technology mapping;
D O I
10.1109/mwscas.2019.8885132
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Quantum computers capable of practical information processing are emerging rapidly. As these devices become more advanced, tools will be needed for converting generalized quantum algorithms into formally-verified forms that are executable on real quantum machines. In this work, a prototype tool is presented that transforms quantum algorithms into executable specifications where optimization procedures yield 9-24 % cost improvement on a range of benchmarks. Additionally, the tool incorporates formal verification internally with Quantum Multiple-valued Decision Diagrams to confirm that the generated technology-dependent executable is functionally equivalent to the original, technology-independent algorithm. Experimental results are provided that target the Rigetti family of quantum processing units although the tool may also target other architectures.
引用
收藏
页码:73 / 76
页数:4
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