VLSI Implementation of Incremental Fixed-Complexity LLL Lattice Reduction for MIMO Detection

Lenstra-Lenstra-Lovasz (LLL) algorithm is a common technique for lattice reduction (LR) aided multiple-input multiple-output (MIMO) detectors. This paper presents the first VLSI implementation of a recently published Incremental fixed-complexity LLL algorithm (Incremental fcLLL) with fewer iterations than other existing fcLLL algorithms. We propose a modified Incremental fcLLL algorithm with simplified size reduction and Siegel condition as well as the designed two-angle complex Givens rotation for column swap, which eliminates all computationally intensive operations. By exploiting the proposed modified algorithm in a pipelined architecture, the implementation on a Xilinx Virtex-5 FPGA demonstrates a throughput of 26 cycles per matrix and near 8 M matrices per second, significantly outperforming the existing FPGA solutions.