Energy Efficient Techniques using FFT for Deep Convolutional Neural Networks

被引:0
|
作者
Nhan Nguyen-Thanh [1 ]
Han Le-Duc [1 ]
Duc-Tuyen Ta [1 ]
Van-Tam Nguyen [1 ,2 ]
机构
[1] Univ Paris Saclay, CNRS, LTCI, Telecom ParisTech, F-75013 Paris, France
[2] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Deep convolutional neural networks (CNNs) has been developed for a wide range of applications such as image recognition, nature language processing, etc. However, the deployment of deep CNNs in home and mobile devices remains challenging due to substantial requirements for computing resources and energy needed for the computation of high-dimensional convolutions. In this paper, we propose a novel approach designed to minimize energy consumption in the computation of convolutions in deep CNNs. The proposed solution includes (i) an optimal selection method for Fast Fourier Transform (FFT) configuration associated with splitting input feature maps, (ii) a reconfigurable hardware architecture for computing high-dimensional convolutions based on 2D-FFT, and (iii) an optimal pipeline data movement scheduling. The FFT size selecting method enables us to determine the optimal length of the split input for the lowest energy consumption. The hardware architecture contains a processing engine (PE) array, whose PEs are connected to form parallel flexible-length Radix-2 single-delay feedback lines, enabling the computation of variable-size 2D-FFT. The pipeline data movement scheduling optimizes the transition between row-wise FFT and column-wise FFT in a 2D-FFT process and minimizes the required data access for the element-wise accumulation across input channels. Using simulations, we demonstrated that the proposed framework improves the energy consumption by 89.7% in the inference case.
引用
收藏
页码:231 / 236
页数:6
相关论文
共 50 条
  • [41] Advancements in the future of automating micromanipulation techniques in the IVF laboratory using deep convolutional neural networks
    Victoria S. Jiang
    Deeksha Kartik
    Prudhvi Thirumalaraju
    Hemanth Kandula
    Manoj Kumar Kanakasabapathy
    Irene Souter
    Irene Dimitriadis
    Charles L. Bormann
    Hadi Shafiee
    Journal of Assisted Reproduction and Genetics, 2023, 40 : 251 - 257
  • [42] Comparison of techniques for radiometric identification based on deep convolutional neural networks
    Baldini, G.
    Gentile, C.
    Giuliani, R.
    Steri, G.
    ELECTRONICS LETTERS, 2019, 55 (02) : 90 - +
  • [43] Energy Efficient Convolutional Neural Networks for EEG Artifact Detection
    Khatwani, Mohit
    Hosseini, M.
    Paneliya, H.
    Hairston, W. David
    Waytowich, Nicholas
    Mohsenin, Tinoosh
    2018 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS): ADVANCED SYSTEMS FOR ENHANCING HUMAN HEALTH, 2018, : 499 - 502
  • [44] An Energy-Efficient Deep Learning Processor with Heterogeneous Multi-Core Architecture for Convolutional Neural Networks and Recurrent Neural Networks
    Shin, Dongjoo
    Lee, Jinmook
    Lee, Jinsu
    Lee, Juhyoung
    Yoo, Hoi-Jun
    2017 IEEE SYMPOSIUM IN LOW-POWER AND HIGH-SPEED CHIPS (COOL CHIPS), 2017,
  • [45] Efficient scale estimation methods using lightweight deep convolutional neural networks for visual tracking
    Seyed Mojtaba Marvasti-Zadeh
    Hossein Ghanei-Yakhdan
    Shohreh Kasaei
    Neural Computing and Applications, 2021, 33 : 8319 - 8334
  • [46] Efficient scale estimation methods using lightweight deep convolutional neural networks for visual tracking
    Marvasti-Zadeh, Seyed Mojtaba
    Ghanei-Yakhdan, Hossein
    Kasaei, Shohreh
    NEURAL COMPUTING & APPLICATIONS, 2021, 33 (14): : 8319 - 8334
  • [47] An Energy-Efficient and Flexible Accelerator based on Reconfigurable Computing for Multiple Deep Convolutional Neural Networks
    Yang, Chen
    Zhang, HaiBo
    Wang, XiaoLi
    Geng, Li
    2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 1389 - 1391
  • [48] Implementation of energy-efficient fast convolution algorithm for deep convolutional neural networks based on FPGA
    Li, W. -J.
    Ruan, S. -J.
    Yang, D. -S.
    ELECTRONICS LETTERS, 2020, 56 (10) : 485 - 487
  • [49] COSY: An Energy-Efficient Hardware Architecture for Deep Convolutional Neural Networks based on Systolic Array
    Yin, Chen
    Chen, Qiang
    Tian, Miren
    Ji, Mohan
    Zou, Chenglong
    Wang, Yin'an
    Wang, Bo
    2017 IEEE 23RD INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS (ICPADS), 2017, : 180 - 189
  • [50] Energy-Efficient Architecture for FPGA-based Deep Convolutional Neural Networks with Binary Weights
    Duan, Yunzhi
    Li, Shuai
    Zhang, Ruipeng
    Wang, Qi
    Chen, Jienan
    Sobelman, Gerald E.
    2018 IEEE 23RD INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING (DSP), 2018,