SAR plus ΔΣ ADCs with open-loop integrator using dynamic amplifier

This paper proposes and discusses SAR+Delta Sigma ADCs with open-loop integrators for low power, high speed, and low noise sensing systems. The integrator uses an open-loop architecture and dynamic amplifier to realize high speed and low power complete integration. Two prototype ADCs have been developed for general purpose and for CMOS image sensors. A high dynamic range of 84 dB and a high Schreier's FoM of 173 dB have achieved. Furthermore, a high FoM over 170 dB is maintained across a wide range of sampling rate from 2.5 MS/s to 25 MS/s. The SAR+Delta Sigma ADC for CMOS image sensors can reduce the noise down to 66 mu V.