Low-Power and Low-Noise Programmable Frequency Dividers in a 130 nm SiGe BiCMOS Technology

被引:0
|
作者
Ergintav, Arzu [1 ]
Herzel, Frank [1 ]
Borngraeber, Johannes [1 ]
Ng, Herman Jalli [1 ]
Kissinger, Dietmar [1 ,2 ]
机构
[1] IHP, Technol Pk 25, D-15236 Frankfurt, Oder, Germany
[2] Tech Univ Berlin, Einsteinufer 17, D-10587 Berlin, Germany
关键词
frequency divider; SiGe BiCMOS; programmable divider; ECL logic; frequency synthesizer; phase-locked loop; GHZ;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Two programmable frequency dividers for fractional-N frequency synthesizers are presented. The input frequency range is from 1 GHz to 10 GHz for both circuits, which were manufactured in a 130 nm SiGe BiCMOS technology. The first divider (divider1) has divisor values ranging from 32 to 127 and operates with a single supply voltage VCC between 2.2 V and 4 V, while the divisor value range for the second one (divider2) is from 32 to 63 and the supply voltage operational range is between 3.0 V and 3.6 V. The divider1 and divider2 draw 100 mA from a 2.5 V supply and 26 mA from a 3 V supply, respectively. The dividers' phase noise contribution referred to the output of a 10 GHz PLL is lower than -108 dBc/Hz at 10 kHz offset and -116.5 dBc/Hz at 1MHz offset. This makes the dividers suitable for low-noise fractional-N phase-locked loops using a conventional CMOS phase-frequency detector.
引用
收藏
页码:105 / 108
页数:4
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