共 50 条
- [41] Data Compression Using Content Addressable Memories SOFT COMPUTING SYSTEMS, ICSCS 2018, 2018, 837 : 193 - 199
- [44] ERROR-FREE DECODING FOR FAILURE - TOLERANT MEMORIES IEEE COMPUTER GROUP NEWS, 1970, 3 (03): : 18 - &
- [46] Construction of polyvalent error control codes for multilevel memories ICECS 2000: 7TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS & SYSTEMS, VOLS I AND II, 2000, : 751 - 754
- [47] Limited Magnitude Error Correction using OLS Codes for Memories with Multilevel Cells 2017 IEEE 35TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2017, : 391 - 394
- [48] A Novel Soft Error Tolerant FPGA Architecture 2016 IFIP/IEEE INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2016,
- [49] Design of Memories with Concurrent Error Detection and Correction by Nonlinear SEC-DED Codes Journal of Electronic Testing, 2010, 26 : 559 - 580
- [50] A soft error tolerant LUT cascade emulator PROCEEDINGS OF THE 15TH ASIAN TEST SYMPOSIUM, 2006, : 115 - +