A 0.18-μm CMOS Dual-Band Frequency Synthesizer With Spur Reduction Calibration

被引：27

作者：

Chen, Yang-Wen ^{[1
,2
]}

Yu, Yueh-Hua ^{[1
,2
]}

Chen, Yi-Jan Emery ^{[1
,2
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Grad Inst Commun Engn, Taipei 10617, Taiwan

[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan

来源：

IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | 2013年 / 23卷 / 10期

关键词：

Charge-pump (CP) current calibration; frequency synthesizer; phase-locked loop (PLL); spur suppression; WIRELESS LAN; DIVIDER;

D O I：

10.1109/LMWC.2013.2279113

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This letter presents a 0.18 mu m CMOS dual-band frequency synthesizer with charge-pump current mismatch calibration to reduce reference spurs. To enhance calibration accuracy the high-resolution phase detector (HRPD) is incorporated in this work. The measured output spur level is less than -63 dBc after the calibration circuits are activated and the reference spur reduction is more than 5.6 dB throughout the whole frequency range. The frequency synthesizer draws 16 mA from a 1.8 V power supply, and the covered frequency bands are 5.18-5.32 GHz and 5.74-5.82 GHz.

引用

页码：551 / 553

页数：3

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