On-Line Software-Based Self-Test of the Address Calculation Unit in RISC Processors

被引：0
|
作者：
Bernardi, P. [1 ]
Ciganda, L. [1 ]
de Carvalho, M. [1 ]
Grosso, M. [1 ]
Lagos-Benites, J. [1 ]
Sanchez, E. [1 ]
Reorda, M. Sonza [1 ]
Ballan, O. [2 ]
机构：
[1] Politecn Torino, Dipartimento Automat & Informat, Turin, Italy
[2] STMicroelect, Milan, Italy
来源：
2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS) | 2012年
关键词：
SoC; pipelined processors; on-line testing; SBST;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Software-based Self-Test (SBST) can be used during the mission phase of microprocessor-based systems to periodically assess the hardware integrity. However, several constraints are imposed to this approach, due to the coexistence of test programs with the mission application. This paper proposes a method for the generation of SBST programs to test on-line the Address Calculation Unit of embedded RISC processors, which is one of the most heavily impacted by the on-line constraints. The proposed strategy achieves high stuck-at fault coverage on both a MIPS-like processor and an industrial 32-bit pipelined processor; these two case studies show the effectiveness of the technique and the low effort.
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页数：6
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