On-Line Software-Based Self-Test of the Address Calculation Unit in RISC Processors

被引：0
|
作者：
Bernardi, P. [1 ]
Ciganda, L. [1 ]
de Carvalho, M. [1 ]
Grosso, M. [1 ]
Lagos-Benites, J. [1 ]
Sanchez, E. [1 ]
Reorda, M. Sonza [1 ]
Ballan, O. [2 ]
机构：
[1] Politecn Torino, Dipartimento Automat & Informat, Turin, Italy
[2] STMicroelect, Milan, Italy
来源：
2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS) | 2012年
关键词：
SoC; pipelined processors; on-line testing; SBST;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Software-based Self-Test (SBST) can be used during the mission phase of microprocessor-based systems to periodically assess the hardware integrity. However, several constraints are imposed to this approach, due to the coexistence of test programs with the mission application. This paper proposes a method for the generation of SBST programs to test on-line the Address Calculation Unit of embedded RISC processors, which is one of the most heavily impacted by the on-line constraints. The proposed strategy achieves high stuck-at fault coverage on both a MIPS-like processor and an industrial 32-bit pipelined processor; these two case studies show the effectiveness of the technique and the low effort.
引用
收藏
页数：6
相关论文
共 50 条
  • [1] Effective software-based self-test strategies for on-line periodic testing of embedded processors
    Paschalis, A
    Gizopoulos, D
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 578 - 583
  • [2] Effective software-based self-test strategies for on-line periodic testing of embedded processors
    Paschalis, A
    Gizopoulos, D
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2005, 24 (01) : 88 - 99
  • [3] A Processor Shield for Software-Based On-Line Self-Test
    Lin, Ching-Wen
    Chen, Chung-Ho
    2016 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), 2016, : 149 - 152
  • [4] An on-line software-based self-test framework for microprocessor cores
    Benso, Alfredo
    Bosio, Alberto
    Prinetto, Paolo
    Savino, Alessandro
    IEEE DTIS: 2006 INTERNATIONAL CONFERENCE ON DESIGN & TEST OF INTEGRATED SYSTEMS IN NANOSCALE TECHNOLOGY, PROCEEDINGS, 2006, : 394 - 399
  • [5] Systematic Software-Based Self-Test for Pipelined Processors
    Gizopoulos, Dimitris
    Psarakis, Mihalis
    Hatzimihail, Miltiadis
    Maniatakos, Michail
    Paschalis, Antonis
    Raghunathan, Anand
    Ravi, Srivaths
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2008, 16 (11) : 1441 - 1453
  • [6] Systematic software-based self-test for pipelined processors
    Psarakis, Mihalis
    Gizopoulos, Dimitris
    Hatzimihail, Miltiadis
    Paschalis, Antonis
    Raghunathan, Anand
    Ravi, Srivaths
    43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006, 2006, : 393 - +
  • [7] Design for testability of software-based self-test for processors
    Nakazato, Masato
    Ohtake, Satoshi
    Inoue, Michiko
    Fujiwara, Hideo
    PROCEEDINGS OF THE 15TH ASIAN TEST SYMPOSIUM, 2006, : 375 - +
  • [8] On-Line Software-based Self-Test for ECC of Embedded RAM Memories
    Restifo, M.
    Bernardi, P.
    De Luca, S.
    Sansonetti, A.
    2017 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT), 2017, : 82 - 87
  • [9] A Software-Based Self-Test Methodology for On-Line Testing of Data TLBs
    Theodorou, G.
    Chatzopoulos, S.
    Kranitis, N.
    Paschalis, A.
    Gizopoulos, D.
    2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2012,
  • [10] A Software-Based Self-Test Methodology for On-Line Testing of Processor Caches
    Theodorou, G.
    Kranitis, N.
    Paschalis, A.
    Gizopoulos, D.
    2011 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2011,
12345