Failure Analysis for Ultra Low Power Nano-CMOS SRAM Under Process Variations

被引：0
|
作者：
Singh, Jawar [1 ,2 ]
Mathew, Jimson [1 ,2 ]
Pradhan, Dhiraj K. [1 ,2 ]
Mohanty, Saraju P. [2 ]
机构：
[1] Univ Bristol, Dept Comp Sci, Bristol BS8 1TH, Avon, England
[2] Univ North Texas, Dept Comp Sci & Engn, Denton, TX 76203 USA
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2008年
关键词：
D O I：
10.1109/SOCC.2008.4641522
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Several design metrics have been used in the past to evaluate the SRAM cell stability. However, most of them fail to provide the exact stability figures as shown in this paper. Therefore, we investigate new stability metrics and report the stability analysis for typical a SRAM cell. In particular, a concept called power metric is introduced. From this metric we derive two new stability figures; static power noise margin (SPNM) and write trip power (WTP). It is shown that these new figures provide better cell stability analysis. Furthermore, we have exhaustively analyzed the impact of different parameters variations such as cell ratio, supply voltage V(id and threshold voltage V-th on SPNM and WTP. Statistical models for estimating SPNM and WTP from intra-die Vth variations are presented. The estimated results match well with the Monte Carlo (MC) simulations.
引用
收藏
页码：251 / +
页数：2
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