Rapid Prototyping of Sub-band Acoustic Echo Cancellers on FPGA Platforms

The paper focuses on a rapid prototyping technique of an acoustic echo canceller implemented on an FPGA platform. The goal is to reduce design, optimization and implementation cost and execution time. In complex signal processing applications, high-order adaptive filter structures suffer from decreased convergence speed and high computational complexity. The sub-band adaptive filtering technique is able to eliminate these disadvantages. The execution time of the echo cancellation in an acoustic enclosure is decreased using multi-rate digital signal processing. To speed-up the execution time of a common acoustic echo canceller, the sub-band decomposition of the source signal is proposed. Here, this procedure is implemented using the Xilinx System Generator library. The hardware implementation of the well-known NLMS adaptive algorithm was carried out. Moreover, the FIR filters in the analysis and synthesis banks are designed with the window method (using the Kaiser window), as the determination of the filter's coefficients is an important procedure to eliminate the alias. The alias occurs due to the usage of multi-rate systems. Hardware implementations that test the behavior of the proposed system were tested for nonstationary input signals. Results show superior tracking abilities of the designed system. Also, an estimation of the FPGA resources is established in each case. The ML501 Xilinx FPGA development board was used for its specific digital signal processing facilities.