Writing P4 compiler backend for packet processing engines

The advent of P4 as a protocol-independent and platform-independent network packet processing language has revolutionized the way networks are designed and the way networking devices are programmed. There are few programmable devices, whether ASICs or FPGA-based devices, that are designed with P4 programmability as the end goal right from the beginning. As a consequence, although these packet processing engines are programmable, writing a P4 compiler for these targets requires overcoming some technical challenges. Our team has worked on a variety of packet processing pipelines in recent years, in this article, we are presenting some of these challenges as well as the solutions we found to work around them.