Residue Number System Arithmetic Inspired Hopping Pilot Pattern Design for Cellular Downlink OFDMA

被引：0
|
作者：
Zhu, Dalin [1 ]
Natarajan, Balasubramaniam [2 ]
机构：
[1] NEC Labs China, 11F Bldg A,Innovat Plaza TusPk, Beijing 100084, Peoples R China
[2] Kansas State Univ, Dept Elect & Comp Engn, Manhattan, KS 66506 USA
来源：
2010 WIRELESS TELECOMMUNICATIONS SYMPOSIUM (WTS) | 2010年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, a novel hopping pilot pattern design method is proposed for downlink multi-cell OFDMA. Specifically, residue number system (RNS) arithmetic is invoked as a tool for constructing pilot patterns with equidistant sampling in both time and frequency domains, and limited mutual interference. Compared to Costas array-based pilot patterns, RNS-based method generated more unique pilot patterns, providing additional degrees of freedom for identifying cells/devices in a multi-cell mult-antenna environment.
引用
收藏
页数：6
相关论文
共 50 条
  • [41] Design of a Residue Number System Based Linear System Solver in Hardware
    Bucek, Jiri
    Kubalik, Pavel
    Lorencz, Robert
    Zahradnicky, Tomas
    JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2017, 87 (03): : 343 - 356
  • [42] Design of a Residue Number System Based Linear System Solver in Hardware
    Jiří Buček
    Pavel Kubalík
    Róbert Lórencz
    Tomáš Zahradnický
    Journal of Signal Processing Systems, 2017, 87 : 343 - 356
  • [43] DESIGN AND SIMULATION OF COMPUTER OPERATING ON RESIDUE-NUMBER SYSTEM
    LAURINI, R
    BENEVENT, J
    FRECON, L
    REVUE FRANCAISE D AUTOMATIQUE INFORMATIQUE RECHERCHE OPERATIONNELLE, 1971, 5 (NB3): : 87 - 107
  • [44] Residue Number System Design Automation for Neural Network Acceleration
    Lin, Liang-Yu
    Schroff, Jerrae
    Lin, Tsu-Ping
    Huang, Tsung-Chu
    2020 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - TAIWAN (ICCE-TAIWAN), 2020,
  • [45] Design of Large Polyphase Filters in the Quadratic Residue Number System
    Cardarilli, Gian Carlo
    Nannarelli, Alberto
    Oster, Yann
    Petricca, Massimo
    Re, Marco
    2010 CONFERENCE RECORD OF THE FORTY FOURTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS (ASILOMAR), 2010, : 410 - 413
  • [46] Variation-tolerant design using Residue Number System
    Kouretas, Ioannis
    Paliouras, Vassilis
    PROCEEDINGS OF THE 2009 12TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, ARCHITECTURES, METHODS AND TOOLS, 2009, : 157 - 163
  • [47] Analysis and Design of Residue Number System Based Building Blocks
    Akhter, Shamim
    Raturi, Gaurav
    Khan, Shaheen
    2018 5TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN), 2018, : 441 - 445
  • [48] Efficient wavelet Architectures using field-programmable logic and residue number system arithmetic
    Ramírez, J
    Meyer-Baese, U
    García, A
    INDEPENDENT COMPONENT ANALYSES, WAVELETS, UNSUPERVISED SMART SENSORS, AND NEURAL NETWORKS II, 2004, 5439 : 222 - 232
  • [49] High-Performance Computation in Residue Number System Using Floating-Point Arithmetic
    Isupov, Konstantin
    COMPUTATION, 2021, 9 (02) : 1 - 15
  • [50] Error detection of arithmetic circuits using a residue checker with signed-digit number system
    Wei, SG
    Shimizu, K
    2001 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2001, : 72 - 77
12345