Simulation study on FinFET with tri-material gate

被引：0
|
作者：
Li, Cong [1 ]
Zhuang, Yiqi [1 ]
Zhang, Li [1 ]
机构：
[1] Xidian Univ, Sch Microelect, Xian 710071, Peoples R China
来源：
2012 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID STATE CIRCUIT (EDSSC) | 2012年
关键词：
FinFET; numerical simulation; tri-material gate; short-channel effects; hot-carrier effects;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a novel tri-material gate (TMG) FinFET device is proposed. Using three-dimensional (3-D) device simulator, hot-carrier effects and short-channel effects of TMG FinFET are investigated and compared with that of dual-material gate FinFET and conventional FinFET. Numerical simulation results shows that TMG FinFET exhibits significantly improved performance in terms of surface potential, electric field and carrier velocity distribution.
引用
收藏
页数：3
相关论文
共 50 条
  • [41] The development of a tri-material system and appropriate bonding parameters for the thermal bonding of flat leads
    Coughlan, FM
    Lewis, HJ
    JOURNAL OF MATERIALS PROCESSING TECHNOLOGY, 2004, 153 (1-3) : 240 - 246
  • [42] Effect of air spacer on analog performance of underlap tri-gate FinFET
    Gupta, Shikhar
    Nandi, Ashutosh
    SUPERLATTICES AND MICROSTRUCTURES, 2017, 109 : 693 - 701
  • [43] Impact of Active Surface Area on Performance and Reliability of Tri-gate FinFET
    Yang, Yi-Lin
    Chuang, Chiao-Feng
    Lai, Chih-Jui
    Zhang, Wenqi
    Hsu, Yun-Hsuan
    Tsai, Chia-Jung
    Lin, Wei-De
    Lin, Meng-Yen
    Yeh, Wen-Kuan
    SENSORS AND MATERIALS, 2019, 31 (07) : 2237 - 2244
  • [44] A new two-dimensional analytical subthreshold behavior model for short-channel tri-material gate-stack SOI MOSFET's
    Chiang, Te-Kuang
    MICROELECTRONICS RELIABILITY, 2009, 49 (02) : 113 - 119
  • [45] Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET
    Es-Sakhi, Azzedin
    Chowdhury, Masud
    MICROELECTRONICS JOURNAL, 2017, 62 : 30 - 37
  • [46] A NOVEL BULK-FINFET WITH DUAL-MATERIAL GATE
    Hong, Yang
    Guo, Yufeng
    Yang, Hui
    Yao, Jiafei
    Zhang, Jun
    Ji, Xincun
    2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2014,
  • [47] Aerospace Electronic and Photonic Packaging: Predicted Thermal Stresses in Bi-and Tri-Material Assemblies
    Suhir, E.
    Nicolics, J.
    Bechou, L.
    2014 IEEE AEROSPACE CONFERENCE, 2014,
  • [48] Investigation on Effect of Temperature on Dual Gate Material Gate/Drain Underlap Germanium FinFET
    Das, Rajashree
    Baishya, Srimanta
    JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2018, 13 (07) : 980 - 985
  • [49] Effect of Temperature, Doping and Gate Material Engineering on Tri-Gate SOI nFinFET Performance Through TCAD Simulation
    Panda, Sridhar
    Parida, Rajat Subhra
    Dora, G. Chiranjibi
    Swain, Raghunandan
    Panigrahy, Asisa Kumar
    Aduri, Kishore Reddy
    Suresh, M.
    TRANSACTIONS ON ELECTRICAL AND ELECTRONIC MATERIALS, 2024, 25 (05) : 600 - 607
  • [50] Modeling, Simulation and Performance Analysis of Drain Current for Below 10 nm Channel Length Based Tri-Gate FinFET
    Suparna Panchanan
    Reshmi Maity
    Srimanta Baishya
    Niladri Pratap Maity
    Silicon, 2022, 14 : 11519 - 11530
12345