A general and efficient clocking scheme for majority logic in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is a nanotechnology with characteristics of high speed, high density, and low power consumption to be one of the strong alternatives to replace traditional CMOS in the future in theory. Its primitive is a majority gate, instead of AND/OR logic in CMOS, which can reduce the complexity of a system and thus its overhead. In this paper, a general and efficient clocking scheme to facilitate the design of circuits using majority gates in QCA is proposed as their scale extends. Each clock zone in this scheme is an octagon adjacent to the other three zones. This results in four input and two output directions in clock zones 0 and 2 to design circuits with majority gates, two input and four output directions in clock zones 1 and 3 to improve the flexibility of circuit routing. Besides, this scheme utilizes the flexible feedback paths for sequential circuits, equivalent clock zones, and elastic QCA wires for efficiently wiring circuits. This paper then takes a one-bit full adder and an SR-latch as examples to show the generality and efficiency of the proposed clocking scheme in designing combinational and sequential circuits, respectively. An arithmetic unit is also taken as an example to illustrate its high expansibility in designing larger circuits. Experimental results show that the proposed clocking scheme is more suitable for QCA circuit design in contrast to previous clocking schemes.