A Study in Functional Verification of ASIP

Functional verification has become the bottleneck in designing of Application Specific Instruction-Set Processor (ASIP). The paper presents a functional verification methodology with great efficiency in designing of ASIP based on hardware structure and instruction-set, which is composed of the component-level verification, the instruction-level verification and the FPGA-based prototype system verification. Experimental results show the methodology has distinctly increased the coverage in the component-level verification and the instruction-level verification comparing with the traditional methodology.