Multiplexer and Memory-Efficient Circuits for Parallel Bit Reversal

被引：4
|
作者：
Garrido, Mario [1 ]
机构：
[1] Linkoping Univ, Dept Elect Engn, S-58183 Linkoping, Sweden
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2019年 / 66卷 / 04期
关键词：
Bit reversal; FFT; pipelined architecture;
D O I：
10.1109/TCSII.2018.2880921
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This brief presents novel circuits for calculating the bit reversal on parallel data. The circuits consist of delays/memories and multiplexers, and have the advantage that they requires the minimum number of multiplexers among circuits for parallel bit reversal so far, as well as a small total memory.
引用
收藏
页码：657 / 661
页数：5
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