An on-chip phase compensation technique in fractional-N frequency synthesis

Fractional-N frequency synthesis relaxes the phase-locked loop (PLL) design constraints to achieve a low noise performance while providing the same channel spacing. Inherent spurs generated by this system can be reduced with various techniques. The proposed architecture effectively compensates the periodic phase error in the time domain so that it is useful with widely used charge-pump PLLs. An on-chip tuning by a delay-locked loop (DLL) is also provided to make the system less dependent on the output frequency and process variations without using any external element. Simulation results show that the fractional spurs can be completely removed with charge-pump PLLs when ideal matching is assumed.