A Threshold-Embedded Offset Calibration Technique for Folding Flash ADCs

被引:0
|
作者
Tang, Tzu-Yi [1 ]
Zeng, Jhao-Wei [1 ]
Chen, Kevin [2 ]
Tsai, Tsung-Heng [1 ]
机构
[1] Natl Chung Cheng Univ, Dept Elect Engn, Chiayi, Taiwan
[2] Ind Tech Res Inst, Info & Comm Res Lab, Hsinchu, Taiwan
关键词
NM DIGITAL CMOS;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A threshold-embedded offset calibration technique for inverter-based analog-to-digital converter (ADC) is presented. This work presents a background calibration technique for trimming the input-referred offsets of the comparators without interrupting the ADC's normal operation. Moreover, a folding flash architecture is employed to save the conversion power. The proposed calibration approach is based on the time-domain comparison. The random input-referred offsets of the comparators are converted to phase difference and detected by time-domain comparators. Simulation results show that the proposed compensation technique is validated. After calibration, the effective number of bits (ENOB) can be significantly improved from 3.4 bit to 5.7 bit.
引用
收藏
页数:4
相关论文
共 50 条
  • [1] A Threshold-Embedded Offset Calibration Technique for Inverter-Based Flash ADCs
    Chan, Chi-Hang
    Zhu, Yan
    Chio, U-Fat
    Sin, Sai-Weng
    Seng-Pan, U.
    Martins, R. P.
    53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 489 - 492
  • [2] Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs
    Keskin, Gokce
    Proesel, Jonathan
    Plouchart, Jean-Olivier
    Pileggi, Lawrence
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (08) : 1904 - 1918
  • [3] A low power offset voltage calibration method for flash ADCs
    Chatterjee, Shatadal
    Roy, Sounak
    INTEGRATION-THE VLSI JOURNAL, 2023, 88 : 58 - 69
  • [4] A Background Calibration Technique for Fully Dynamic Flash ADCs
    Shu, Yun-Shiang
    Tsai, Jui-Yuan
    Chen, Ping
    Lo, Tien-Yu
    Chiu, Pao-Cheng
    2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
  • [5] A Background Calibration Technique for Fully Dynamic Flash ADCs
    Shu, Yun-Shiang
    Tsai, Jui-Yuan
    Chen, Ping
    Lo, Tien-Yu
    Chiu, Pao-Cheng
    2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
  • [6] DFT Technique for Quick Characterization of Flash Offset in Pipeline ADCs
    Nair, Pradeep
    Viswanathan, Nagarajan
    2015 28TH INTERNATIONAL CONFERENCE ON VLSI DESIGN (VLSID), 2015, : 375 - 380
  • [7] An Offset Double Conversion Technique for Digital Calibration of Pipelined ADCs
    Peng, Bei
    Li, Hao
    Lin, Pingfen
    Chiu, Yun
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2010, 57 (12) : 961 - 965
  • [8] Bulk Voltage Trimming Offset Calibration for High-Speed Flash ADCs
    Yao, Junjie
    Liu, Jin
    Lee, Hoi
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2010, 57 (02) : 110 - 114
  • [9] A Digital Calibration Technique for Folding-Integration/Cyclic Cascaded ADCs
    Wang, Tongxi
    Khandaker, Amin M. R.
    Yasutomi, Keita
    Kawahito, Shoji
    2015 IEEE 58TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2015,
  • [10] A Novel Digital Calibration Technique for Gain and Offset Mismatch in Parallel TIΣΔ ADCs
    Beydoun, Ali
    Nguyen, Van-Tam
    Loumeau, Patrick
    2010 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, 2010, : 4158 - 4161