The fabrication of metallic nanotransistors

Extensive research studies have been devoted into the field of scaling down transistor size for ultra high density integrated circuits over the last three decades. It has been suggested that for the smallest possible scale of MOS transistor channel, a channel conductance close to that of a metal is required [1]. Metallic nanotransistors are based on Held effect transistor made from metallic nanowires. This type of transistor operates by governing the flow of electrons through a narrow channel. In the fabrication of metallic nanotransistors, an electron beam lithography process has been developed to fabricate structures at the sub30nm scale using silver nanowires on SiN substrate. The single pass line exposure technique in electron beam lithography has been employed to define patterns of transistor structure as small as 20.2nm dimensions. This paper details the design and fabrication techniques of metallic nanotransistors. The limiting issues for writing sub30nm structures using EBL such as the charging effect of insulating materials, the proximity effects, and the single pass exposures are discussed.