Lowering the Error Floors of Low-Density Parity-Check Codes with Additional Check Nodes

被引：0
|
作者：
Yuan, Dongming [1 ]
Li, Lu [1 ]
Liu, Yuanan [1 ]
机构：
[1] Beijing Univ Posts & Telecommun, Sch Elect Engn, Beijing, Peoples R China
来源：
2017 IEEE INFORMATION THEORY WORKSHOP (ITW) | 2017年
基金：
中国国家自然科学基金;
关键词：
Low-density parity-check codes; bit recovery; trapping sets; error floor; additional check nodes;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
This paper proposes a novel scheme for bit recovery of Low-Density Parity-Check (LDPC) Codes. Firstly, the most erroneous and the most reliable bits are located by searching the codeword bits. Subsequently, new check nodes are added to connect them, thus the negative effects of the most erroneous bits along with the corresponding trapping sets are avoided. Eventually, the BER performance is dramatically improved in the error-floor region according to the simulated results. This idea could be a more concise and simple alternative to weaken the effects of trapping sets in LDPC applications.
引用
收藏
页码：146 / 150
页数：5
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