A low power and compact desktop ATM PMD

被引：0
|
作者：
Wakayama, Y
Nakano, F
Takeuchi, J
Honda, N
Ishii, K
Sakamoto, T
Fujii, T
机构：
来源：
PROCEEDINGS OF THE IEEE 1997 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 1997年
关键词：
D O I：
10.1109/CICC.1997.606641
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A PMD sublayer circuit for 25.6 Mb/s ATM interface has been developed in a 0.35 mu m CMOS process. Although it contains a UTP 100m cable equalizer circuit and a clock recovery circuit, a low power 74mW and a small die area 2.52 mm(2) are achieved. With the circuit, a six port 25.6 Mb/s ATM interface chip has been realized.
引用
收藏
页码：331 / 334
页数：4
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