System Architecture Design of PCIe Root Complex Based on SOPC

PCIe bus is widely applied because of its high-bandwidth, high reliability and low cost characteristic. Research on PCIe root complex architecture based on FPGA begin to receive attentions. However, current methods are usually expensive, code closure and poor flexibility. A new open source PCIe root system architecture based on Xilinx SOPC platform is proposed in this paper. The system is mainly composed of AXI-PCIe bridge,, AXI interconnect, processing subsystem and DDR3 memory. The processing system runs the embedded Linux operating system for controlling and management functions. The AXI-PCIe bridge communicates with the specific PCIe endpoint device and provides the conversion logic for the PCIe domain address and the AXI domain address. They are connected by high performance AXI interconnect. This paper uses the gigabit ethernet card and network bandwidth testing tools to verify the proposed hardware and software design method. The architecture of this approach has the advantages of simple structure, powerful performance and easy expansion, which provides a feasible solution for new high-performance servers and large-scale PLC systems.