A Fast Recursive Algorithm and Architecture for Pruned Bit-reversal Interleavers

In this paper, pruned bit-reversal permutations employed in variable-length interleavers and their associated fast pruning algorithms and architectures are considered. Pruning permutations is mathematically formulated as a counting problem in a set of k integers and any subset of a consecutive integers under some permutation, where integers from this subset that map into indices less than some beta < k are to be counted. A solution to this problem using sums involving integer floors and related functions is proposed. It is shown that these sums can be evaluated recursively using integer operations. Specifically, a mathematical treatment for bit-reversal permutations (BRPs) and their permutation statistics are presented. These permutations have been mainly addressed using numerical techniques in the literature to speed up in-place computations of fast Fourier and related transforms. Closed-form expressions for BRP statistics including inversions, serial correlations, and a new statistic called permutation inliers that characterizes the pruning gap of pruned interleavers, are derived. Using the inliers statistic, a recursive algorithm that computes the minimum number of inliers in a pruned BR interleaver (PBRI) in logarithmic time complexity is presented. This algorithm enables parallelizing a serial PBRI algorithm by any desired parallelism factor by computing the pruning gap in lookahead rather than a serial fashion, resulting in significant reduction in interleaving latency and memory overhead. Extensions to 2-D block and stream interleavers are also presented. Moreover, efficient hardware architectures for the proposed algorithms employing simple logic gates are presented. Simulation results of interleavers employed in modern communication standards demonstrate 3 to 4 orders of magnitude improvement in interleaving time compared to existing approaches.