Comprehensive Compact Electro-Thermal GaN HEMT Model

In this work we demonstrate a semi-empirical GaN HEMT model implemented in Verilog-A format. The model captures accurately the DC operation of test devices fabricated and measured at IMS CHIPS including the thermal effects. In addition, the off-state leakage current is physically modeled as a space-charge limited current prior to the onset of the physical breakdown. The dynamic current recovery of the transistor after stress bias is physically included by implementing the model in the form of a finite state machine, capturing the memory effect of the device. The drain current is modified to be a summation of multiple exponential terms, each corresponding to a given trapping center. This model can be used to predict the overall performance of the GaN HEMTs based on the epitaxial material composition or to infer the material composition and quality based on the measured device characteristics.