Hidden faults in FPGA-built digital components of safety-related systems

This paper is devoted to a problem of the hidden faults, which can be accumulated in digital components of safety related systems during a long term normal mode and reduce fault tolerance of circuits and safety of system in the most responsible emergency mode. This problem connected with low checkability of array structures traditionally used in digital components of safety related systems. The problem of the hidden faults can he solved in case of digital component implementation on base of bitwise pipelines. They process data in the series codes which do not leave the place for the hidden faults. Whether bitwise pipelines can compete with array structures in throughput and energy consumption? The comparative analysis in throughput and energy consumption of pipeline and array structures on the example of the bitwise pipeline and iterative array multipliers implemented in FPGA by CAD of Altera is offered. Faults of the general signals, such as synchronization violation, can also show the hidden behavior which is not always detected in processing of serial codes. Monitoring of the general signals oldie digital circuit on the basis oldie analysis of its power consumption is offered. The comparative analysis of bitwise pipeline and iterative array multipliers on FPGA in suitability to monitoring of the general signals on the basis of the assessment of power consumption is carried out.