A 1.5V, wide-input range, high-bandwidth, CMOS four-quadrant analog multiplier

被引：19
|
作者：
Sawigun, Chutham [1 ]
Mahattanakul, Jirayuth [1 ]
机构：
[1] Mahanakorn Univ Technol, Dept Elect Engn, Fac Engn, Bangkok 10530, Thailand
来源：
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 | 2008年
关键词：
D O I：
10.1109/ISCAS.2008.4541918
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A low-voltage low-power CMOS four quadrant analog multiplier based directly on a cross-coupled squarer topology and suitable for the deep submicron technology is presented. Simulation results using 0.35-mu m process parameters show that, when operated under a 1.5V single supply, the proposed multiplier consumes 290 mu W of quiescent power, its linear range with respect to both differential input voltages is +/- 0.4 V and its bandwidth is about 100MHz.
引用
收藏
页码：2318 / 2321
页数：4
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