Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs

被引：68

作者：

Karmakar, Supriya ^{[1
,2
]}

Chandy, John A. ^{[1
]}

Jain, Faquir C. ^{[1
]}

机构：

[1] Univ Connecticut, Dept Elect & Comp Engn, Storrs, CT 06269 USA

[2] Intel Corp, Hillsboro, OR 97124 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2013年 / 21卷 / 05期

关键词：

Integrated circuit; quantum dot gate field effect transistor (QDGFET); ternary logic; VLSI; NEGATIVE DIFFERENTIAL RESISTANCE; RESONANT-TUNNELING TRANSISTOR; PERFORMANCE; FABRICATION; MODFET; HEMT; WELL;

D O I：

10.1109/TVLSI.2012.2198248

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we discuss logic circuit designs using the circuit model of three-state quantum dot gate field effect transistors (QDGFETs). QDGFETs produce one intermediate state between the two normal stable ON and OFF states due to a change in the threshold voltage over this range. We have developed a simplified circuit model that accounts for this intermediate state. Interesting logic can be implemented using QDGFETs. In this paper, we discuss the designs of various two-input three-state QDGFET gates, including NAND- and NOR-like operations and their application in different combinational circuits like decoder, multiplier, adder, and so on. Increased number of states in three-state QDGFETs will increase the number of bit-handling capability of this device and will help us to handle more number of bits at a time with less circuit elements.

引用

页码：793 / 806

页数：14

共 50 条

[11] Quantum Dot Gate InGaAs FETs
Jain, F.
Alamoody, F.
Suarez, E.
Gogna, M.
Chan, P-Y.
Karmakar, S.
Fikiet, J.
Miller, B.
Heller, E.
NANOTECH CONFERENCE & EXPO 2009, VOL 1, TECHNICAL PROCEEDINGS: NANOTECHNOLOGY 2009: FABRICATION, PARTICLES, CHARACTERIZATION, MEMS, ELECTRONICS AND PHOTONICS, 2009, : 598 - +
[12] Design of Combinational Logic circuits for Low power Reversible Logic circuits in Quantum Cellular Automata
Anand, I. Vivek
Kamaraj, A.
2014 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2014,
[13] Artificial intelligence techniques applied to design of logic circuits based on ternary quantum-dot cellular automata
Janez, M.
Bajec, I. Lebar
Pecar, P.
Zimic, N.
Mraz, M.
MICROPROCESSES AND NANOTECHNOLOGY 2007, DIGEST OF PAPERS, 2007, : 138 - 139
[14] Design of memristor-based combinational logic circuits
Tao, Zeheng
Wang, Lei
Sun, Chuanyang
Wan, Xiang
Liu, Xiaoyan
Cai, Zhikuang
Lian, Xiaojuan
IEICE ELECTRONICS EXPRESS, 2024, 21 (03):
[15] Design of Memristor-Based Combinational Logic Circuits
Liu, Gongzhi
Shen, Shuhang
Jin, Peipei
Wang, Guangyi
Liang, Yan
CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2021, 40 (12) : 5825 - 5846
[16] Design of Memristor-Based Combinational Logic Circuits
Gongzhi Liu
Shuhang Shen
Peipei Jin
Guangyi Wang
Yan Liang
Circuits, Systems, and Signal Processing, 2021, 40 : 5825 - 5846
[17] Realization of combinational logic circuits using standard functions in quantum dot cellular automata
Chakrabarty, Ratna
Mandal, Niranjan Kumar
NANOSYSTEMS-PHYSICS CHEMISTRY MATHEMATICS, 2021, 12 (05): : 583 - 597
[18] Multiple Valued Logic Using 3-State Quantum Dot Gate FETs
Chandy, John A.
Jain, Faquir C.
38TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2008), 2008, : 186 - 190
[19] Design of Subthreshold Adiabatic Logic based Combinational and Sequential Circuits
Kalyani, P.
Kumar, P. Satish
Sekhar, P. Chandra
2017 INTERNATIONAL CONFERENCE ON EMERGING TRENDS & INNOVATION IN ICT (ICEI), 2017, : 9 - 14
[20] Diagnosis method for single logic design errors in gate-level combinational circuits
NEC Corp, Kanagawa, Japan
Systems and Computers in Japan, 1997, 28 (06): : 30 - 38

← 1 2 3 4 5 →