Generator of predictive verification pattern using vision system based on higher-order local autocorrelation

Although lithography conditions, such as NA, illumination condition, resolution enhancement technique (RET), and material stack on wafer, have been determined to obtain hotspot-free wafer images, hotspots are still often found on wafers. This is because the lithography conditions are optimized with a limited variety of patterns. For 40 nm technology node and beyond, it becomes a critical issue causing not only the delay of process development but also the opportunity loss of the business. One of the easiest ways to avoid unpredictable hotspots is to verify an enormous variety of patterns in advance. This, however, is time consuming and cost inefficient. This paper proposes a new method to create a group of patterns to cover pattern variations in a chip layout based on Higher-Order Local Autocorrelation (HLAC), which consists of two phases. The first one is the "analyzing phase" and the second is the "generating phase". In the analyzing phase, geometrical features are extracted from actual layouts using the HLAC technique. Those extracted features are statistically analyzed and define the "feature space". In the generating phase, a group of patterns representing actual layout features are generated by correlating the feature space and the process margin. By verifying the proposed generated patterns, the lithography conditions can be optimized efficiently and the number of hotspots dramatically reduced.