An OR-Type Cascaded Match Line Scheme for High-Performance and EDP-Efficient Ternary Content Addressable Memory

Although feathered with high search speed, NOR-type match line in ternary content addressable memory (TCAM) can hardly be cascaded to achieve low power due to its parallel connection nature. In this paper, a novel OR-type cascaded match-line scheme is proposed, which serially connects the OR-type match line segments by nature, realizing high search speed and low power. For pre-layout simulation, the proposed 64-word x 72-bit TCAM with 3 stages, based on 0.13-um 1.2-V SMIC process, achieves 0.41fJ/bit/search with 0.48 ns search time, which delivers an EDP (energy-delay-product) reduction of 43.6% and 15.8% over conventional pre-charge high NOR-type match line architecture and AND-type match-line approach, respectively. The post-layout simulation shows that the proposed scheme realizes 0.58fJ/bit/search within 1.13 ns searching time.