Design of 8 Bit Interpolating Flash ADC Based on CMOS Technology

被引：0
|
作者：
Bu, Dan [1 ]
Li, Liangyu [1 ]
Qiu, Chengjun [1 ]
机构：
[1] Heilongjiang Univ, Key Lab Elect Engn Heilongjiang Prov, Harbin, Peoples R China
来源：
3RD INTERNATIONAL CONFERENCE ON MATERIALS SCIENCE AND MECHANICAL ENGINEERING, (ICMSME 2016) | 2016年
关键词：
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
An 8 bit 1GHz interpolating flash ADC was designed with 0.18um CMOS technology, which was composed of band gap voltage reference, resistance divided network, preamplifier, interpolating resistance structure, high speed latched comparator, bubble code elimination circuit, and encoder circuit. The ADC was simulated at power voltage of 1.8V and sampling frequency of 1GHz, the results showed that the value of the INL and DNL were 0.35LSB and 0.2LSB respectively, SNR was 44.3dB, SNDR was 41.6dB, SFDR was 54.35dB, ENOB was 7.1bit, power consumption was 234mW, and the layout area was 2.36mm(2).
引用
收藏
页码：121 / 124
页数：4
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