BiCMOS gate array circuits

被引：0
|
作者：
Hu, XH
Wang, MY
Zhang, M
机构：
来源：
1996 2ND INTERNATIONAL CONFERENCE ON ASIC, PROCEEDINGS | 1996年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
BICMOS gate array circuits and macrocell libraries are designed and fabricated through 2.0 mu m BiCMOS standard processes. The average gate delay time is as follows: BiCMOS 21 stage inverter, 1.1ns; BiCMOS 21 stage oscillator, 1.1ns; BiCMOS 21 stage NAND, 1.3ns; BiCMOS 21 stage NOR 1.4ns. BICMOS 500 gate array circuits are optimized and 2000 gate array circuits are designed. The delay time of BiCMOS is less than CMOS with large load capacitance.
引用
收藏
页码：333 / 335
页数：3
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