Performance of a-Si:H photodiode technology-based advanced CMOS active pixel sensor imagers

Amorphous silicon photodiode technology is a very attractive option for image array integrated circuits because it enables large die-size reduction and higher light collection efficiency than c-Si arrays. The concept behind the technology is to place the photosensing element directly above the rest of the circuit, thus eliminating the need to make areal tradeoffs between photodiode and pixel circuit. We have developed an photodiode array technology that is fully compatible with a 0.35um CMOS process to produce image sensors arrays with 10-bit dynamic range that are 30% smaller than comparable c-Si photodiode arrays. The work presented here will discuss performance issues and solutions to lend itself to cost-effective high-volume manufacturing. The various methods of interconnection of the diode to the array and their advantages will be presented. The effect of doped layer thickness and concentration on quantum efficiency, and the effect of a-Si:H defect concentration on diode performance will be discussed. The photodiode dark leakage current density is about 80 pA/cm(2), and its absolute quantum efficiency peaks about 85% at 550 nm. These sensors have 50% higher sensitivity, and 2x lower dark current when compared to bulk silicon sensors of the same design. The cell utilizes a 3 FET design, but allows for 100% photodiode area due to the elevated nature of the design. The VGA (640x480), array demonstrated here uses common intrinsic and p-type contact layers, and makes reliable contact to those layers by use of a monolithic transparent conductor strap tied to vias in the interconnect.