Design of a Capacitive DAC Mismatch Calibrator for Split SAR ADC in 65 nm CMOS

被引：0
|
作者：
Anh Trong Huynh [1 ]
Hoa Thai Duong [2 ]
Hoang Viet Le [1 ]
Skafidas, Efstratios [1 ]
机构：
[1] Natl ICT Australia, Sydney, NSW, Australia
[2] Univ Melbourne, Dept Elect & Elect Engn, Melbourne, Vic 3010, Australia
来源：
2013 ASIA-PACIFIC MICROWAVE CONFERENCE PROCEEDINGS (APMC 2013) | 2013年
基金：
澳大利亚研究理事会;
关键词：
Analog to digital converter; successive approximation register; capacitor mismatch; complementary metal oxide semiconductor;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents the design and implementation of a capacitive digital to analog converter (CDAC) mismatch calibrator used in split successive approximation resistor (SAR) analog to digital converter (ADC) in a 65 nm complementary metal oxide semiconductor (CMOS) process. The calibrator adopts a compensation capacitor connected to the least significant bit (LSB) capacitor array to calibrate the mismatch between the lowest-bit capacitor of the most significant bit (MSB) array and the LSB array. An 11-bit 50-MS/s split SAR ADC using this calibrator was developed. The measurement results show that the calibration process improves the differential nonlinearity (DNL) value from -1.2/+1.9 LSBs to -0.55/+0.75 LSBs and the integral nonlinearity (INL) value from -1.9/+2.12 LSBs to -0.95/+0.99 LSBs. The calibrated ADC achieves a signal to noise and distortion ratio (SNDR) of 58.95 dB near the Nyquist frequency and an effective number of bits (ENOB) of 9.5 bits.
引用
收藏
页码：503 / 505
页数：3
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