Implementation of HDLC Controller Design using Verilog HDL

被引：0

作者：

Nagpurwala, Armaan Hasan ^{[1
]}

Sundaresan, C. ^{[1
]}

Chaitanya, C. V. S. ^{[1
]}

机构：

[1] Manipal Univ, SOIS, Manipal, India

来源：

2013 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS AND SYSTEM ENGINEERING (ICEESE) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

HDLC Protocol is used to send the data in the form of frames, a controller controls the flow of data in DATA LINK LAYER of OSI model. HDLC protocol is used to transmit frames in logic link layer of Data link Layer. HDLC frame consists of an 8 bit Flag bit as 01111110, followed by control bits, information bits, fcs bits (CRC), address bits and terminates with flag bit. It involves processing of data before transmission, termed as Zero Stuffing, which is a special feature of HDLC protocol. A FIFO is used to transmit the data in the order of First In First Out. When complete data is transmitted, FIFO generates empty signal and the transmission of fcs, control, information and address bits begins. In the receiver side, detection of flag bits marks the beginning of new frame and zero unstuffing of data is performed. The unstuffed data is stored in variable length memory. The architecture for HDLC protocol has been proposed in this paper. The proposed model is implemented and verified using Verilog HDL.

引用

页码：7 / 10

页数：4

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