Centralized Parallel Form of Pattern Matching Algorithm in Packet Inspection by Efficient Utilization of Secondary Memory in Network Processor

被引：0
|
作者：
Raja, N. Kannaiya [1 ]
Arulanandam, K. [2 ]
RajaRajeswari, B. [1 ]
机构：
[1] Arulmigu Meenakshi Amman Coll Engg, CSE Dept, Near Kanchipuram, India
[2] Ganadipathy Tulsis Jain Engn Coll, CSE Dept, Vellore, Tamil Nadu, India
来源：
GLOBAL TRENDS IN COMPUTING AND COMMUNICATION SYSTEMS, PT 1 | 2012年 / 269卷
关键词：
Intrusion detection; Network Security; Pattern matching; Packet payload; Packet inspection;
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
The Network detection engine have capable of inspecting the packet and find out increasing number of network worms and virus. The high level of network providing packet inspection in detection system and the network equipments applies the predefined pattern to identify and manage the monitor packet over the network. Therefore consequently the emerging high level network 'equipments need to contribute pattern matching and packet inspection. However, searching for patterns at multiple offsets in entire content of network packet requires more processing power than most general purpose processor can provide. We present a novel architecture for programmable centralized parallel pattern matching algorithm for efficient packet inspection with network processor. We mapped our centralized multi parallel pattern matching algorithm [CNMPPMA] for filter packet in parallel. The simulation result reveals that CNMPPMA significantly improves the matching performance.
引用
收藏
页码：671 / +
页数：3
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