Fully Integrated CMOS Doherty Power Amplifier with Network Matching Optimization for Die Size Reduction

被引：0

作者：

Carneiro, Marcos L. ^{[1
,2
]}

Deltimple, Nathalie ^{[2
]}

Carvalho, Paulo H. P. ^{[1
]}

Belot, Didier ^{[3
]}

Kerherve, Eric ^{[2
]}

机构：

[1] Univ Brasilia, Dept Elect Engn, Brasilia, DF, Brazil

[2] Univ Bordeaux, IMS Lab, Talence, France

[3] STMicroelectronics, Crolles, France

来源：

2014 44TH EUROPEAN MICROWAVE CONFERENCE (EUMC) | 2014年

关键词：

CMOS integrated circuit; design methodology; power amplifier; circuit optimization;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Impedance network topology optimization method is proposed for saving die area and increasing performance. The technique was applied on a fully integrated Doherty Power Amplifier design in 65nm CMOS technology. Measurement results achieve a constant 24% PAE performance over a 7 dB backoff, P-out of 23.4dBm and 15dB of gain. The optimization allowed the reduction of the number of inductors which reduced in 59% the expected die area and also increased the PAE mean performance in 5% on the high power stage and the P-out in 2dB.

引用

页码：1269 / 1272

页数：4

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